In the early days of modern computing, magnetic memory was traditionally associated with core memory. Core memory was quickly made obsolete by the advent of semiconductor memory. As a result, more recently magnetic memory has been almost exclusively associated with disk drives. In a disk drive, a platter coated with a magnetic material rotates in proximity to one or more heads. Depending on the electrical signals applied to the heads, the heads function to write to or read from the disk by affecting, or sensing, respectively, the alignment of a portion of the magnetic material on the platter. While this has served many applications well for an extended period, the moving parts and mechanical aspects of disk drives limit their desirability in many applications which may involve impacts or other stresses which might damage the relatively delicate disk drive.
More recently, solid state magnetic devices have been developed which take advantage of the GMR, or giant magnetoresistive, effect. An example of a structure in which the GMR effect may be observed consists of a stack of four magnetic thin films: a free magnetic layer, a nonmagnetic conducting layer, a magnetic pinned layer, and an exchange layer. Magnetic orientation of the pinned layer is fixed and is held in place by the exchange layer. By applying an external magnetic field, the magnetic orientation of the free layer may be changed with respect to the magnetic orientation of the pinned layer, such that two states can exist. These states can therefore represent two logical values. The change in magnetic orientation results in a significant change in the resistance of the metallic layered structure, and that resistance can be sensed to indicate the stored logical value.
The GMR effect has been used in what are referred to as MRAM, or Magnetoresistive Random Access Memory devices. These devices offer some tantalizing benefits over disk drives, because they do not involve any moving parts. A typical MRAM structure is shown in FIG. 1, in which two layers of ferromagnetic material are separated by a thin insulation layer to form a magnetic tunnel junction. The direction of the domains in the bottom layer is fixed, while those in the top layer can switch when a magnetic field is applied. Whether a 1 or 0 is stored depends on whether the two layers' magnetic domains point in the same or opposite directions.
Writing data into the MRAM cell involves applying current to the bit and digit lines. The magnetic fields created by the two currents line up the magnetic domains in the desired direction. In the case of FIG. 1, current from left to right in the bit line 10 and into the page in the digit line 15 align the free ferromagnetic layer 20 in the same direction as the fixed layer 25. An insulator 30 is positioned between the free layer 20 and the fixed layer 25. The directions of the free and fixed layers are as shown by the arrows on the respective layers, although the orientation of the fixed layer could be in either direction. It will be appreciated by those skilled in the art that the layers 20, 25 and 30 form a magnetic tunnel junction.
Reading the cell involves measuring the resistance of the tunnel junction. It is low if the domains in the two layers are parallel, high if they are antiparallel.
In a typical MRAM structure, a low coercivity ferromagnetic material is used for writing, and a GMR stack is used for both reading and writing to the cell. Further, the GMR stack is typically in contact with the metal lines used to provide drive signals, and at least one drive transistor per cell is required. Unfortunately, these characteristics of MRAM devices present some significant challenges to their broad adoption.
For example, one of the challenges involved in the integration of MRAM technology is temperature incompatibility with the CMOS process. Several standard CMOS process steps occur at or above 400° C. However, the magnetoresistive (MR) effect of typical Magnetic Tunnel Junction (MTJ) material begins to degrade at temperatures above 300° C. and drops sharply by 400° C. Producing MRAMs using MTJs is a key process challenge since the tunneling dielectric is just about 1.5 nm thick. As a result, the lack of compatibility between the magnetic materials used in MRAM and the temperature management required for CMOS processing makes it difficult to integrate MRAM into existing CMOS processes.
Another limitation of conventional MRAM devices is that the erase process is relatively slow and inefficient. In an MRAM device, the erase process is essentially the reverse of the write process; that is, in order to program an MRAM memory bit, current is passed through the conductive lines in one direction. To erase that MRAM memory bit, current is passed through the same conductive lines in the opposite direction. This essentially limits each erase step to a small sector size, which is undesirable because it is slow and inefficient.
As a result there has been a need for a solid state magnetic memory device which is compatible with CMOS processes. In addition, there has been a need for a solid state magnetic memory device which offers a large difference in the resistance between the parallel and antiparallel states of the memory cell.